1. Technical Field
Exemplary embodiments of the inventive concept relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that is configured to save power.
2. Discussion of Related Art
The time taken to output data after a read command is applied to a semiconductor memory device may be referred to as read latency and the time taken to receive external data after a write command is applied to the semiconductor device may be referred to as write latency. The read latency and the write latency may be expressed by a predetermined number of clock periods. In a semiconductor memory device, after the read latency is set to a predetermined value, the write latency may be defaulted to be equal to the read latency. A read operation of the semiconductor memory may involve decoding an address applied along with a read command, selecting a memory cell corresponding to the address, sensing data of the selected memory cell, and externally outputting the sensed data. Thus, the read operation may require a minimum latency of, for example, four clock periods. Accordingly, the read latency cannot be set to fewer clock periods (e.g., two clock periods) than the minimum latency. In contrast, during a write operation, the semiconductor memory device may receive external data as soon as a write command is applied. Accordingly, the write latency may be set to a smaller number of clocks (e.g., two clocks) relative to the read latency. Accordingly, the efficiency of the semiconductor memory may be reduced when the write latency is equated to the read latency, especially in high-speed semiconductor memory devices.
However, when the write latency is set to a small value (e.g., three clocks or less), it may be difficult to synchronize the write clock signal with an external clock signal and generate a stable write clock signal until the semiconductor memory device externally receives the data. When the write clock signal is not stabile, the semiconductor memory device may malfunction.
A semiconductor device may maintain a write clock signal to be continuously enabled during an active mode when the write latency is set to a small value to reduce malfunctions. However, when the write clock signal is maintained in this manner, the semiconductor memory device uses more power.